1. Field of the Invention
The present invention relates to integrated circuit fabrication and, in particular, to fabrication of stacked capacitor structures utilizing thin film ceramic oxide.
2. Description of the Related Art
A. Electronic Ceramic Oxides
Electronics ceramic oxides have been used in electrical applications for many years as bulk ceramics due to their high dielectric constant. However, electronic ceramic oxides also display a spontaneous polarization characteristic which can be reversed upon the application of an electric field. Many new applications have been recently developed to take advantage of this polarization characteristic using thin film oxide ceramics (&lt;1.0 .mu.m). For example, thin film electronic ceramic oxides have been used for non-volatile memory applications, including EEPROM, EPROM, flash memory, magnetic core memory, plated wire memory, and SRAM and DRAM replacements. Other devices have also been developed which utilize thin film electronic ceramic oxides, such as surface acoustic wave (SAW) generators, electrooptic devices, fully integrated microsensors, microacuators, micromanipulators, and infrared detectors.
A variety of electronic ceramic oxides exist which can be used for thin film devices, including any of the over 400 ferroelectrics materials and high temperature superconductors. Of the ferroelectric class, common materials include lead titanate (PT), lead zirconate titanate (PZT), and lanthanum doped lead zirconate titanate (PLZT), along with the barium titanate family (BaTi03), lithium niobate (LiNbO3), potassium niobate (KNb03), tungsten bronzes, lead magnesium niobate (pbMgNb03), and lead scandium niobate (PbScNb03). Typically, the properties of these materials are optimized through deposition technology and subsequent thermal heat treatments.
B. Stacked Capacitors
In solid-state integrated circuit technology, a major design goal is the reduction of the lateral size of the electrical elements comprising the integrated circuit so that more elements can be incorporated into the circuit without increasing its lateral size. One such integrated circuit element is a capacitor.
In reducing the lateral size of a capacitor structure, a primary objective is to maintain the total surface area of the capacitor, thereby maintaining its charge storage capability.
For example, in ferroelectric capacitor structures, which are used as charge storage devices in integrated circuits, maintaining a minimum charge storage capability is particularly important. In a ferroelectric capacitor, the non-volatile charge on the capacitor is used to define a particular memory state. When the total surface area of the capacitor becomes too small, the charge in the capacitor cannot properly be differentiated. This results in unpredictable memory states.
As shown in FIGS. 1A-1C, two semiconductor capacitor structures that have been developed to minimize the lateral use of silicon real estate consumed by the typical planar capacitor are the trench capacitor and the stacked capacitor. As the name implies, the first step in forming a trench capacitor is the formation of a trench in a semiconductor substrate. The bottom electrode is then conformally formed over the sidewalls and the bottom of the trench. Next, a dielectric layer is formed on the lower electrode and then the upper electrode is formed on the dielectric layer.
A stacked capacitor is formed by first creating an electrically conductive pillar that rises above the topography of the surface of the semiconductor substrate. The bottom electrode is then conformally formed over the pillar, followed by formation of a dielectric intermediate plate, and the top electrode.
Stacked capacitors have several advantages over trench capacitors. One primary advantage is that the fabrication of the stacked capacitor is a back-end technology whereas the fabrication of the trench capacitor is a front-end technology. In other words, stacked capacitors are formed during one of the later processing steps in the fabrication of a semiconductor circuit.
A back-end technology allows manufacturers the flexibility of standardizing the early processing steps so that several semiconductor circuits, having a particular front-end design like a MOS or bipolar, may be fabricated from common building blocks. Additionally, since stacked capacitors are formed above the surface topology of the semiconductor substrate, the stacked capacitor may be formed at a variety of locations. For example, stacked capacitors may be formed above the source, drain, and gate of a MOS transistor or above the collector, emitter, and base of a bipolar transistor.
An additional advantage of stacked capacitors over trench capacitors is that, as the technology is pushed to the limits, the trench capacitor must get narrower and deeper. As the trench capacitor gets narrower and deeper, it becomes more difficult to fill up the trenches. This problem is not encountered with the stacked capacitor approach. Even if technologies are developed to fill narrower and deeper trenches, the trench capacitor still consumes more lateral space than the stacked capacitor because the trench capacitor is placed next to a transistor structure whereas the stacked capacitor is placed above the transistor.
Ceramic oxide stacked capacitors in semiconductor integrated circuits, however, have proved to be difficult to fabricate. A stacked capacitor with a ceramic oxide layer is comprised of a conductive pillar, a bottom electrode, a thin-film ceramic oxide layer which is conformally formed over the outer surface of the bottom electrode, and a top electrode which covers the ceramic oxide layer.
After the conductive pillar and the bottom electrode have been formed, one method of forming the thin-film ceramic oxide layer is to spin on a ceramic oxide sol-gel. The difficulty, however, is that the spin-on ceramic oxide film, like all the other spin-on films, tends to planarize and fill up gaps. This makes it difficult to use spin-on films to obtain a uniform thickness of the ceramic oxide over the bottom electrode. Thus, it appears that a spin-on ceramic oxide film is incompatible with the stacked capacitor approach. Therefore, there is a need to provide a method for forming a conformal spin-on ceramic oxide layer on the surface of a bottom electrode.
Another problem with spin-on ceramic oxides is that the characteristics of the ceramic oxide degrade because of its interactions with silicon oxide and silicon nitride films which are commonly used as passivation layers. A passivation layer is a layer of material which is deposited over the entire top surface of the circuit to insulate and protect the circuit from mechanical and chemical damage. Silicon nitride is the preferred passivation material because it is compatible with inexpensive plastic packages. Since the ceramic oxide interacts with nitride, other passivation materials must be used which then require the use of a more expensive ceramic package. Thus, there is a need to have a ceramic oxide capacitor integrated circuit technology which is compatible with inexpensive plastic packaging techniques.